The present invention relates to the art of semiconductor fabrication and packaging.
Semiconductor chips commonly incorporate a large number of active electronic devices such as transistors and diodes, passive devices such as resistors and capacitors, and larger devices made up of combinations of such active and passive devices as, for example, logic gates, memory cells, amplifiers and the like, all formed within a single, integral body. Most commonly, the body is formed from silicon, although other materials such as diamond and compound semiconductors can be used. The active devices in the chip typically are provided in one or more layers extending parallel to the front and back surfaces of the chip.
The various electronic devices of the chip typically are interconnected with one another by metallic conductors such as traces extending within the chip in the horizontal or xe2x80x9cxxe2x80x9d and xe2x80x9cyxe2x80x9d direction and metallic vias extending in the vertical or xe2x80x9czxe2x80x9d direction. Typically, the traces and vias are formed of conductive material deposited during fabrication of the chip as, for example, aluminum or polysilicon. The traces and vias used to interconnect the electronic elements of the chip with one another complicate design and fabrication of the chip.
The traces which are fabricated during manufacture of the chip do not always provide optimum electrical characteristics. For example, traces formed from aluminum have a relatively high resistivity. Although processes for fabricating traces in a chip from low-resistivity metals such as copper are known, these processes impose special requirements in chip fabrication. Further, even if a low-resistivity metal is employed, the size and hence the cross-sectional area of traces which can be accommodated within a chip are subject to severe limitations. Traces extending within a chip often follow indirect routes because other elements of the chip lie in a direct route between the electronic elements connected by the traces.
Additionally, chips must be connected to external circuit elements. In the conventional approach to chip packaging, each chip is incorporated in a separate package bearing leads or other external connecting elements. Contacts on the surface of the chip are connected to these external connecting elements. The external connecting elements on the package are connected to a conventional circuit board or other circuit-bearing substrate. Alternatively, several chips may be mounted in a single package, commonly referred to as a xe2x80x9cmultichip module.xe2x80x9d These chips may be connected to one another and to a common set of external connecting elements, so that the entire assembly can be mounted to the substrate as a unit. In yet another alternative, the chip itself is attached directly to the substrate.
As described in Arima et al., U.S. Pat. No. 5,281,151, a rigid ceramic board may be provided with a set of xe2x80x9cthin filmxe2x80x9d circuit layers overlying the ceramic board. The thin film layers include metallic traces on a material such as polyimide which has a relatively low dielectric constant. A chip is mounted to the thin film layers by solder balls in engagement with contacts on the chip. A signal can be routed from point to point within the chip along a signal path through a solder ball at one location on the chip, along a metallic trace of the thin film element and back into the chip through a solder ball at another location on the chip. The thin film layer assertedly provides low resistance and relatively rapid signal transmission between elements of the chip. In other embodiments, the interconnections can be formed within the ceramic circuit board itself, and the polyimide layers may be omitted.
Rostoker et al. U.S. Pat. Nos. 5,756,395 and 5,640,049 disclose generally similar interconnect structures associated with semiconductor chips. These devices rely on solder-bonding the interconnect structure to contacts on the active semiconductor chip itself. This in turn requires bulk melting of the solder during assembly, which in turn imposes significant constraints on the number and placement of the interconnects to provide sufficient space between interconnects and to avoid shorting between adjacent contacts.
Rai et al., U.S. Pat. No. 4,818,728 describes a process for making a composite semiconductor chip by use of projecting studs on one element received in pools of solder held in recesses on the surface of the opposing element, which suffers from similar drawbacks. The Rai et al. patent also mentions the use of a dielectric xe2x80x9cbonding agentxe2x80x9d on the surfaces of one semiconductor element to bond with the opposing element. Pace, U.S. Pat. No. 5,866,441 discloses the use of gold or similar ductile xe2x80x9cprotruberancesxe2x80x9d projecting from the surface of a chip which can be bonded to similar xe2x80x9cprotruberancesxe2x80x9d on a packaging module by processes such as thermocompression or ultrasonic bonding or by soldering. The resulting structure has a large gap between the chip and the module. To form a sealed structure, Pace uses a seal around the outside of the areas bearing the contacts. The horizontal dimensions of the chip and module must be increased to provide for this external seal, and the resulting structure contains a large air-filled gap.
As described in preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390, 5,518,964, 5,688,716 and International Publications WO 96/02068 and WO 97/11486, the disclosures of which are all incorporated by reference herein, it is desirable to provide interconnections between the contacts on a chip and external circuitry by providing a further dielectric element, which may be referred to as a xe2x80x9cinterposerxe2x80x9d or xe2x80x9cchip carrierxe2x80x9d having terminals. Terminals on the dielectric element may be connected to the contacts on the chip by flexible leads. The terminals on the dielectric element may be connected to the substrate as, for example, by solder bonding the terminals to contact pads of the substrate. The dielectric element and terminals remain movable with respect to the chip so as to compensate for thermal expansion and contraction of the components. That is, various parts of the chip can move with respect to the terminals as the chip grows and shrinks during changes in temperature. In a particularly preferred arrangement, a compliant dielectric layer is provided as a separate component so that the compliant layer lies between the chip and the terminals. The compliant layer may be formed from a soft material such as a gel, elastomer, foam or the like. The compliant layer mechanically decouples the dielectric element and terminals from the chip and facilitates movement of the terminals relative to the chip. The compliant layer may also facilitate movement of the terminals in the Z direction, towards the chip, which further facilitates testing and mounting of the assembly.
As disclosed in International Publication No. WO 97/40958, the disclosure of which is also incorporated by reference herein, the electrically conductive parts on the dielectric element may be connected to the chip by masses of a fusible, electrically conductive material which is adapted to melt at temperatures encountered during processing or operation of the assembly. These masses may be constrained by a surrounding compliant dielectric material so that they remain coherent while in a molten state. The molten masses provide another form of deformable conductive element, which allows movement of the flexible dielectric element relative to chip. As further disclosed in commonly assigned patents and patent applications, one or more chips may be mounted to a common dielectric element or interposer, and additional circuit elements also may be connected to such a dielectric element. The dielectric element may incorporate conductive traces which form interconnections between the various chips and electronic components of the assembly.
As described in certain preferred embodiments of commonly assigned International Publication WO 98/44564, the disclosure of which is hereby incorporated by reference herein, an interposer which is movable with respect to the chip may itself provide interconnections between devices within a single chip. This provides a uniquely desirable solution in that it facilitates mounting of the chip to an external substrate and also facilitates connections between devices within the chip. In particularly preferred embodiments of the structures taught in the ""486 International Application, the conductive paths within the interposer include multiple conductors and are connected to the chip by leads which also incorporate multiple conductors to provide controlled-impedance connections entire signal paths. This facilitates high-speed signal transmission.
Despite these and other improvements, still further methods and structures for semiconductor chip packaging would be desirable.
One aspect of the invention provides microelectronic assemblies. A microelectronic assembly according to this aspect of the invention desirably includes an active microelectronic element as, for example, a semiconductor chip. The active microelectronic element has an active element body with surfaces including a front surface, one or more active electronic devices in the body and active element contacts exposed to the front surface. The assembly according to this aspect of the invention also includes an interconnect element having an interconnect element body formed separately from the active element body. Most preferably, the interconnect element body has a coefficient of thermal expansion substantially matched to the coefficient of thermal expansion of the active element body. The interconnect element desirably has a first surface confronting the front surface of the active element body. The interconnect element most preferably has interconnect conductors carried by the interconnect element body, at least some of the interconnect conductors being connected to at least some of the active element contacts.
The assembly further includes terminals for connection to an external substrate. At least some of the terminals overlies one or more of the surfaces of the interconnect element body, the active element body, or both. For example, the terminals may overlie a second surface of the interconnect element body facing away from the active element body. In another example, the terminals overlie a rear surface of the active element body. The terminals are connected to at least some of the interconnect conductors and are movable with respect to the interconnect element body and the active element body.
The interconnect element body and the active element body can be rigidly connected to one another. This arrangement facilitates the use of small connections to the active microelectronic element, at small center-to-center distances or contact pitch. The interconnect element can provide routing between terminals of the same active microelectronic element as, for example, routing of signals which otherwise would be carried by internal conductors of the chip, as well as connections between the active microelectronic element and the terminals. The movable terminals provide compensation for thermal expansion and contraction when the assembly is mounted to a circuit panel or other substrate.
Another aspect of the invention provides methods of making microelectronic assemblies. A method in accordance with this aspect of the invention desirably includes providing an active microelectronic element including active devices in an active element body and separately providing an interconnect element including an interconnect element body and interconnect conductors having electrical conductivity at least equal to that of copper in an interconnect body. The method further includes joining the interconnect element to the active element so as to connect the interconnect conductors to active devices in the active element. Most preferably, the method includes the further step of connecting terminals to at least some of the interconnect conductors so that the terminals are movable with respect to the interconnect body and so that the terminals are exposed for connection to an external substrate.
Because the interconnect conductors are provided in a separate interconnect body, formation of the interconnect conductors does not influence or impede the processes used to make the active microelectronic element. For example, the difficulties associated with forming copper conductors within the body of a semiconductor wafer do not arise. Yet, the finished assembly can provide benefits such as low-impedance interconnections among active devices within the active element.
Yet another aspect of the invention provides methods of joining microelectronic elements to one another. Methods according to this aspect of the invention desirably include the step of juxtaposing first and second microelectronic elements. The first microelectronic element has a first body with a body surface and with metallic contact bumps projecting from this surface. The second microelectronic element has a second body which has a body surface, recesses in such surface and metallic contact pads disposed in the recesses. The elements are juxtaposed with one another so that the body surfaces confront one another and so that the bumps project into the recesses.
The method further includes bonding the bumps to the contact pads by a substantially solid phase bonding process while urging the bodies toward one another so that at least some of said bumps, at least some of said contacts or both deform within said recesses. Optionally, the method includes bonding the body surfaces to one another, most preferably simultaneously with the step of bonding the bumps to the pads.
Preferred methods in accordance with this aspect of the invention can be used to bond small contacts and pads which are disposed at a small contact pitch. These methods can be used, for example, to connect the active microelectronic element to the interconnect element in the methods and assemblies discussed above, and for other purposes. The methods can provide reliable connections despite minor deviations from perfect planarity and dimensions in the elements, bumps and contact pads.